1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof, and in particular to an improved semiconductor package which enhances adhesion between a solder and a package body and improves stability and a fabrication method thereof.
2. Discussion of the Related Art
There is an increasing demand for miniaturization of non-memory products, such as microprocessors and custom semiconductors ASIC. As a result, in order to utilize a plurality of pins, a ball grid array (BGA) arranging a ball-shaped external terminal below a package has become a main semiconductor package.
The BGA takes concepts of a pin grid array (PGA) and a flip chip. Accordingly, a space of a conventional semiconductor package is reduced by approximately 60%, and electrical and thermal execution power is increased by 40%. In case the BGA uses more than 300 pins, it is advantageous in cost as well.
Various chip size package (CSP) techniques have been recently developed to the extent that the semiconductor chip and package are only slightly different in size. The CSP techniques have been rapidly widespread according to the miniaturization, high speed and high integration tendency of the semiconductor, more than the applicants expected.
In addition, a wafer level package technique performing all assembly steps in a wafer state where chips are not cut is acknowledged as the CSP technique for the next generation. A semiconductor assembly process is generally performed after cutting a wafer into respective chips. Conversely, in the wafer level package technique, a series of assembly steps, such as die bonding, wire bonding and molding are carried out in the wafer state where the chips are connected, and thereafter the chips are cut. Accordingly, the wafer level package technique can reduce an entire packaging cost more than the currently-used CSP techniques.
FIG. 1 illustrates a conventional wafer level chip size package (WLCSP). As depicted in FIG. 1, a plurality of chip pads 3 are separately formed on an upper surface of a wafer 1. A passivation layer 5 is formed on the upper surface of the wafer 1 so that a region of an upper surface of the plurality of chip pads 3 are exposed. An under bump metallurgy (UBM) 7 is formed at upper surfaces of the plurality of chip pads 3 exposed through the passivation layer 5. The UBM 7 is formed in order to enhance adhesion between the plurality of chip pads 3 and a solder ball 9 (to be discussed later) and generally consists of a 2- to 3-level metal layer. After forming the UBM 7, a solder paste is coated on upper surfaces of the UBM 7 and the passivation layer 5. The solder ball 9 is formed after a reflow step, thereby fabricating the WLCSP.
One disadvantage of the conventional WLCSP is that adhesion between the solder ball 9 and the UBM 7 is weak. Accordingly, separation may take place due to the weak adhesion between the solder ball 9 and the UBM 7, after constant switching operations of a chip. Therefore, the solder ball 9 may be easily separated from a package body. Another disadvantage of the conventional WLCSP is that materials constituting the UBM 7 are difficult to combine.